The present invention relates to an SCSI (Small Computer System Interface) system and an SCSI controller LSI for controlling the SCSI system.
Heretofore, SCSI controllers have been used extensively to interface devices constituting a small-scale information processing system. FIG. 8 shows a typical system configuration utilizing an SCSI setup. The SCSI (ANSI X3T131-1986) is a collection of interface standards stipulated by the ANSI (American National Standards Institute) to interface personal computers, workstations and their peripherals. What is shown in FIG. 8 is a parallel interface system for data interchange using an SCSI bus 820 comprising nine control buses and nine data buses. Up to eight SCSI-based devices may be configured. Data are exchanged between initiators (host computers) 801 through 803 on the one hand, and targets (peripherals) 804 through 808 on the other.
SCSI controllers 811 through 818 control the SCSI-based transmission of data between the devices connected to the SCSI bus. In many cases, the SCSI controllers 811 through 808 are furnished in the IC form such as LSI's.
FIG. 3 depicts a conventional SCSI controller LSI setup. In the figure, reference numeral 1 is a CPU-side internal bus; 2 is an SCSI-side internal data bus; 3 is a CPU connection bus; 4-1 is an SCSI data bus single end input signal; 4-2 is an SCSI data bus single end output signal; 4-3 is an SCSI control bus single end input signal; and 4-4 is an SCSI control bus single end output signal. A data FIFO (first-in, first out) memory 5 temporarily stores data transferred between the CPU and the SCSI controller to adjust the rate of data transfer therebetween. An internal register 6 accommodates the data provided by the CPU. A parity detector 7 checks for parity data that are input from the SCSI controller or from the MPU (microprocessor unit). Reference numerals 9-1 and 9-3 are SCSI bus receivers, and 9-2 and 9-4 are SCSI bus drivers. A sequencer 8 receives as its input signals the outputs from the internal register 6, parity detector 7 and receiver 9-3, and controls the SCSI bus operation according to the commands placed in command FIFO memories 13 and 14. Reference numeral 11 is an SCSI bus status signal which is output by the receiver 9-3 and which is input to the sequencer 8; 12 is a driver control signal which is output by the sequencer 8 for control over the driver 9-4; and 10 is an interrupt signal sent to the CPU. The command FIFO memories 13 and 14 hold up to two SCSI control commands that are set by the CPU. The FIFO memory 13 is a first-stage FIFO memory that accommodates the currently executing command; the FIFO memory 14 is a second-stage FIFO memory that stores a command waiting to be executed. Status FIFO memories 15 and 16 accommodate up to two results from command execution by the sequencer 8. The status FIFO memory 15 is a first-stage FIFO memory, and the FIFO memory 16 is a second-stage FIFO memory. Interrupt bits 17 and 18 are included in the status FIFO memories 15 and 16, respectively.
FIG. 11 illustrates operation timings of a typical conventional SCSI controller LSI. In FIG. 11, a command 1 is written to the first-stage command FIFO memory 13 by the CPU. A second command 2 from the CPU is written to the second-stage command FIFO memory 14. The sequencer 8 processes the command 1 held in the first-stage command FIFO memory 13. After processing, the sequencer 8 places the end status of the command 1 to the first-stage status FIFO memory 15, and loads the command 2 from the second-stage command FIFO memory 14 to the first-stage command FIFO memory 13. The sequencer 8 then starts processing the command 2 written in the first-stage command FIFO memory 13.
Once the sequencer 8 has placed the end status of the command 1 in the first-stage status FIFO memory 15, an interrupt signal 10 is output to the CPU. On completing the processing of the command 2, the sequencer 8 places the end status of the command 2 into the second-stage status FIFO memory 16. Upon receipt of the interrupt signal 10, the CPU reads the end status of the command 1 from the first-stage status FIFO memory 15, thereby knowing the result of execution of the previously issued command 1. This prompts the end status of the command 2 held in the second-stage status FIFO memory 16 to be loaded into the first-stage status FIFO memory 15. With the end status of the command 2 loaded into the first-stage status FIFO memory 15, another interrupt signal 10 is output to the CPU. On receiving the second interrupt signal 10, the CPU reads the end status of the command 2 held in the first-stage status FIFO 15, thereby knowing the result of execution of the previously issued command 2. If the command 1 ends abnormally, the sequencer 8 generates an abnormal end interruption to the CPU and automatically clears the command 2.
Table 1 below lists typical commands that the CPU issues to the SCSI controller LSI. In the cable, the second column from left contains the commands and the rightmost column describes the operation specified by each command.
TABLE 1 ______________________________________ No. Command Name Operation ______________________________________ 1 Select With ATN Execute the sequence "arbitration Sequence phase .fwdarw. selection phase .fwdarw. message-out phase .fwdarw. command phase." 2 Transfer Exchange data in the phase Information indicated by the target upon initiation (or end with ACK/ asserted in the message-in phase). 3 Message Accepted Negate ACK/. ______________________________________
Below is an example of what takes place when an initiator issues a "Read" command to a target and disconnects for waiting to seek therefrom, with an SCSI controller LSI used as an SCSI adapter for the initiator. In the sequence of FIG. 12, phase transition starts in a bus-free phase, followed by an arbitration phase, a selection phase, a message-out phase, a command phase, a message-in phase and a bus-free phase, in that order. First, the CPU writes to the data FIFO memory 5 transmit data such as "Read" command data for transmission to the target. The CPU then issues a "Select With ATN Sequence" command and a "Transfer Information" command (see Table 1) to the SCSI controller LSI. In turn, the sequencer 8 of the SCSI controller LSI executes the "Select With ATN Sequence" command to control the SCSI bus and run the arbitration phase, selection phase, message-out phase and command phase, in that order. After completing the command phase and negating an ACK/ signal 1201, the sequencer 8 outputs to the first-stage status FIFO memory 15 a code indicating a normal end, sets "1" to the interrupt bit 17, and outputs an interrupt signal 10 to the CPU.
The sequencer 8 then executes the "Transfer Information" command 200, receives one byte of data in the message-in phase, outputs to the second-stage status FIFO memory 16 a code indicating a normal end while asserting the ACK/ signal, and sets "1" to the interrupt bit 18. When the CPU reads the normal end status of the "Select With ATN Sequence" command, the normal status of the "Transfer Information" command held in the second-stage status FIFO memory 16 is loaded into the first-stage status FIFO memory 15. The value of the interrupt bit 18 is loaded into the interrupt bit 17, and another interrupt signal 10 is output to the CPU. When the CPU reads the normal status of the "Transfer Information" command, both the first-stage status FIFO memory 15 and the interrupt bit 17 are cleared, and the interrupt signal 10 is negated.
Next, the CPU reads the input data from the data FIFO memory 5. The CPU issues a "Message Accepted" command to clear the ACK/ signal 1201 in the message-in phase, and issues a "Transfer Information" command 2000 to receive the next one byte. The sequencer 8 executes the "Message Accepted" command, negates the ACK/ signal 1201, outputs to the first-stage status FIFO memory 15 a code indicating a normal end when a REQ/1202 signal is asserted by the target, sets "1" to the interrupt bit 17, and outputs an interrupt signal 10 to the CPU. The sequencer 8 executes the "Transfer Information" command, receives one byte of data in the message-in phase, outputs to the second-stage status FIFO memory 16 a code indicating a normal end while asserting the ACK/ signal 1201, and sets "1" to the interrupt bit 18.
When the CPU starts reading the normal end status of the "Message Accepted" command, the normal status of the "Transfer Information" command stored in the second-stage status FIFO memory 16 is loaded into the first-stage status FIFO memory 15. The value of the interrupt bit 18 is loaded into the interrupt bit 17, and another interrupt signal 10 is output to the CPU. When the CPU reads the normal status of the "Transfer Information" command, both the first-stage status FIFO memory 15 and the interrupt bit 17 are cleared, and the interrupt signal 10 is negated. In addition, the CPU issues a "Message Accepted" command to clear the ACK/ signal 1201 in the message-in phase.
The sequencer 8 executes the "Message Accepted" command, negates the ACK/ signal, outputs to the first-stage status FIFO memory 15 a code indicating a normal end when the target negates a BSY/ signal, sets "1" to the interrupt bit 17, and outputs an interrupt signal 10 to the CPU. When the CPU reads the normal end status of the "Message Accepted" command to verify the normal end thereof, both the first-stage status FIFO memory 15 and the interrupt bit 17 are cleared, and the interrupt signal 10 is negated.
As described, SCSI control sequences of the SCSI controller LSI are generally controlled by the CPU using combinations of general-purpose commands. Individual operation sequences are specified using combinations of a small number of general-purpose commands because using a different command for each SCSI operation sequence will amount to a very large number of commands as a whole. The commands listed in Table 1 are used in combination with other commands in implementing a plurality of SCSI control sequences.
Where conventional SCSI controllers are used, executing a sequence of issuing a "Read" command and receiving data from a target will require the CPU to effect five interruptions in response to five interrupt signals. Under control of conventional SCSI controllers, the CPU is notified of the end status of each and every command by interruption. This is because combinations of commands are used to specify the SCSI control sequences. The result is a large overhead stemming from the interruptions effected during SCSI protocol processing by the CPU.
On the other hand, specifying each SCSI control sequence with a single command will require using a large number of commands in total. The numerous commands will have to be processed by a sequencer of highly complex constitution.
Below is a description of how the conventional SCSI bus and the CPU operate in a sequence of receiving a two-byte message in the message-in phase stipulated by the SCSI protocol. In the message-in phase, if received data are not correct, the SCSI protocol stipulates that an ATN/ signal be asserted before the ACK/ signal is negated. It follows that the SCSI control command must end while the ACK/ signal is being asserted. It also means that the CPU must issue a command to negate the ACK/ signal after reading and verifying the data from the data FIFO memory 5. All this generally amounts to a large overhead in the message-in phase under the SCSI protocol.
FIG. 2 depicts operation sequences of SCSI bus control commands (10h, 12h). FIG. 5 shows a typical SCSI protocol sequence highlighting a portion of the timing chart of FIG. 12. Upon receipt of an interrupt signal 10 indicating the end of the preceding phase, the CPU reads the internal register 6 to verify a normal end, ascertains that the SCSI bus status is in the message-in phase, and issues an SCSI bus control command (10h). When no SCSI bus control command is input, the sequencer 8 waits for an SCSI bus control command to be input while on a path (21) in a state &lt;12&gt;. When the SCSI bus control command (10h) is issued, the sequencer 8 travels a path (22) to reach a state &lt;13&gt;. The sequencer 8 then checks an SCSI bus status signal 11. If, as a result of this check, an IO/ signal is found to be Low and the message-in phase to be in effect, the sequencer 8 travels a path (23) to reach a state &lt;14&gt;, receives a single transfer byte, and asserts the ACK/ signal. The sequencer 8 checks the parity detector 7 next to see if the parity code is normal. If the parity code is found to be normal, the sequencer 8 travels a path (24) to reach a state &lt;15&gt; in which to place a termination interrupt signal in the internal register 6, travels a path (25) to reach a state &lt;16&gt; in which to output an interrupt signal 10 to the CPU, and travels a path (26) to return to the state &lt;12&gt;.
On receiving the interrupt signal 10, the CPU reads the internal register 6 to verify a normal end, reads the message byte from the FIFO memory 5 to ascertain the normal value thereof, and issues an SCSI bus control command (12h). The sequence 8 travels a path (27) to reach a state &lt;17&gt; in which to negate the ACK/ signal. The sequencer 8 then travels a path (28) to reach a state &lt;18&gt; in which to check to see if the REQ/ signal is asserted. Passing through a path (29), the sequencer 8 stays in the state &lt;18&gt; until the REQ/ signal is asserted. Once the REQ/ signal is asserted, the sequencer 8 travels a path (30) to reach a state &lt;19&gt; in which to place a bus service interrupt signal in the internal register 6, and travels a path (31) to reach the state &lt;16&gt; in which to output an interrupt signal 10 to the CPU. The sequencer 8 then travels the path (26) to reach the state &lt;12&gt; again. Upon receipt of the interrupt signal 10, the CPU reads the internal register 6 to verify a normal end, checks to see if the SCSI bus is in the message-in phase, and issues an SCSI bus control command (10h). With the SCSI bus control command (10h) issued, the sequencer 8 travels the path (22) to reach the state &lt;13&gt;. The sequencer 8 then checks the SCSI bus status signal 11. If, as a result of the check, the IO/ signal is found to be Low and the message-in phase to be in effect, the sequencer 8 travels the path (23) to reach the state &lt;14&gt;, receives one-byte transfer data, and asserts the ACK/ signal. Next, the sequencer 8 checks the parity detector 7 to see if the parity code is normal. If the parity code is found to be normal, the sequencer 8 travels the path (24) to reach the state &lt;15&gt;, places a termination interrupt signal in the internal register 6, and travels the path (25) to reach the state &lt;16&gt; in which to output an interrupt signal 10 to the CPU. The sequencer 8 then travels the path (26) to return to the state &lt;12&gt;.
On receiving the interrupt signal 10, the CPU reads the internal register 6 to verify a normal end, reads the message byte from the FIFO memory 5 to ascertain the normal value thereof, and issues an SCSI bus control command (12h). The sequencer 8 travels the path (27) to reach the state &lt;17&gt; in which to negate the ACK/ signal. The sequencer 8 then travels the path (28) to reach the state &lt;18&gt; in which to check to see if the REQ/ signal is asserted. Passing through the path (29), the sequencer 8 stays in the state &lt;18&gt; until the REQ/ signal is asserted. Once the REQ/ signal is asserted, the sequencer 8 travels the path (30) to reach the state &lt;19&gt; in which to place a bus service interrupt signal in the internal register 6, and travels the path (31) to reach the state &lt;16&gt; in which to output an interrupt signal 10 to the CPU. The sequencer 8 then travels the path (26) to return to the state &lt;12&gt;.
As described, a conventional SCSI sequence requires carrying out four interruptions. The interrupt processing has thus turned out to be a major overhead in terms of SCSI protocol processing execution time. In addition, because command execution is terminated by negating the ACK/ signal in other than the message-in phase, it is impossible to generate an attention condition in a desired information transfer phase in order to request a message-out phase.